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- DIGITAL SYSTEM CLOCKING. High-Performance and Low-Power Aspects
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Digital System Clocking: High-Performance and Low-Power Aspects
In electronics and especially synchronous digital circuits , a clock signal historically also known as logic beat  oscillates between a high and a low state and is used like a metronome to coordinate actions of digital circuits. A clock signal is produced by a clock generator.
Circuits using the clock signal for synchronization may become active at either the rising edge, falling edge, or, in the case of double data rate , both in the rising and in the falling edges of the clock cycle. Most integrated circuits ICs of sufficient complexity use a clock signal in order to synchronize different parts of the circuit, cycling at a rate slower than the worst-case internal propagation delays.
In some cases, more than one clock cycle is required to perform a predictable action. As ICs become more complex, the problem of supplying accurate and synchronized clocks to all the circuits becomes increasingly difficult. The preeminent example of such complex chips is the microprocessor , the central component of modern computers, which relies on a clock from a crystal oscillator.
The only exceptions are asynchronous circuits such as asynchronous CPUs. A clock signal might also be gated, that is, combined with a controlling signal that enables or disables the clock signal for a certain part of a circuit.
This technique is often used to save power by effectively shutting down portions of a digital circuit when they are not in use, but comes at a cost of increased complexity in timing analysis.
Most modern synchronous circuits use only a "single phase clock" — in other words, all clock signals are effectively transmitted on 1 wire. In synchronous circuits , a "two-phase clock" refers to clock signals distributed on 2 wires, each with non-overlapping pulses.
Since a gated latch uses only four gates versus six gates for an edge-triggered flip-flop, a two phase clock can lead to a design with a smaller overall gate count but usually at some penalty in design difficulty and performance.
MOS ICs typically used dual clock signals a two-phase clock in the s. These were generated externally for both the and microprocessors. The requires more clock cycles to execute a processor instruction.
Higher speed versions of both microprocessors were released by The requires an external 2-phase clock generator. The MOS Technology uses the same 2-phase logic internally, but also includes a two-phase clock generator on-chip, so it only needs a single phase clock input, simplifying system design.
Some early integrated circuits use four-phase logic , requiring a four phase clock input consisting of four separate, non-overlapping clock signals. Most modern microprocessors and microcontrollers use a single-phase clock. Many modern microcomputers use a " clock multiplier " which multiplies a lower frequency external clock to the appropriate clock rate of the microprocessor.
The vast majority of digital devices do not require a clock at a fixed, constant frequency. As long as the minimum and maximum clock periods are respected, the time between clock edges can vary widely from one edge to the next and back again. Such digital devices work just as well with a clock generator that dynamically changes its frequency, such as spread-spectrum clock generation , dynamic frequency scaling , etc.
Devices that use static logic do not even have a maximum clock period or in other words, minimum clock frequency ; such devices can be slowed and paused indefinitely, then resumed at full clock speed at any later time.
Some sensitive mixed-signal circuits , such as precision analog-to-digital converters , use sine waves rather than square waves as their clock signals, because square waves contain high-frequency harmonics that can interfere with the analog circuitry and cause noise. Such sine wave clocks are often differential signals , because this type of signal has twice the slew rate , and therefore half the timing uncertainty, of a single-ended signal with the same voltage range.
Differential signals radiate less strongly than a single line. Alternatively, a single line shielded by power and ground lines can be used. In CMOS circuits, gate capacitances are charged and discharged continually. A capacitor does not dissipate energy, but energy is wasted in the driving transistors. In reversible computing , inductors can be used to store this energy and reduce the energy loss, but they tend to be quite large.
Alternatively, using a sine wave clock, CMOS transmission gates and energy-saving techniques, the power requirements can be reduced. The most effective way to get the clock signal to every part of a chip that needs it, with the lowest skew, is a metal grid. The whole structure with the gates at the ends and all amplifiers in between have to be loaded and unloaded every cycle. The clock distribution network or clock tree , when this network forms a tree distributes the clock signal s from a common point to all the elements that need it.
Since this function is vital to the operation of a synchronous system, much attention has been given to the characteristics of these clock signals and the electrical networks used in their distribution. Clock signals are often regarded as simple control signals; however, these signals have some very special characteristics and attributes.
Clock signals are typically loaded with the greatest fanout and operate at the highest speeds of any signal within the synchronous system. Since the data signals are provided with a temporal reference by the clock signals, the clock waveforms must be particularly clean and sharp. Furthermore, these clock signals are particularly affected by technology scaling see Moore's law , in that long global interconnect lines become significantly more resistive as line dimensions are decreased.
This increased line resistance is one of the primary reasons for the increasing significance of clock distribution on synchronous performance.
Finally, the control of any differences and uncertainty in the arrival times of the clock signals can severely limit the maximum performance of the entire system and create catastrophic race conditions in which an incorrect data signal may latch within a register.
Most synchronous digital systems consist of cascaded banks of sequential registers with combinational logic between each set of registers. The functional requirements of the digital system are satisfied by the logic stages. Each logic stage introduces delay that affects timing performance, and the timing performance of the digital design can be evaluated relative to the timing requirements by a timing analysis. Often special consideration must be made to meet the timing requirements.
For example, the global performance and local timing requirements may be satisfied by the careful insertion of pipeline registers into equally spaced time windows to satisfy critical worst-case timing constraints. The proper design of the clock distribution network helps ensure that critical timing requirements are satisfied and that no race conditions exist see also clock skew.
The delay components that make up a general synchronous system are composed of the following three individual subsystems: the memory storage elements, the logic elements, and the clocking circuitry and distribution network.
Novel structures are currently under development to ameliorate these issues and provide effective solutions. Important areas of research include resonant clocking techniques, on-chip optical interconnect, and local synchronization methodologies.
From Wikipedia, the free encyclopedia. This article is about timing of electronic circuits. For setting clocks to the correct time of day, see Time signal. Main article: clock multiplier. October [September ]. Archived PDF from the original on Retrieved New York: McGraw-Hill. April 15, These IC produced the two-phase non-overlapping waveforms the and required.
Later Intel produced the clock generator and Motorola produced the MC The Intel and the Motorola include this circuitry on the microprocessor chip. Microcomputer Digest. Cupertino CA: Microcomputer Associates. September Jouppi and Jeffrey Y.
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In electronics and especially synchronous digital circuits , a clock signal historically also known as logic beat  oscillates between a high and a low state and is used like a metronome to coordinate actions of digital circuits. A clock signal is produced by a clock generator. Circuits using the clock signal for synchronization may become active at either the rising edge, falling edge, or, in the case of double data rate , both in the rising and in the falling edges of the clock cycle. Most integrated circuits ICs of sufficient complexity use a clock signal in order to synchronize different parts of the circuit, cycling at a rate slower than the worst-case internal propagation delays. In some cases, more than one clock cycle is required to perform a predictable action. As ICs become more complex, the problem of supplying accurate and synchronized clocks to all the circuits becomes increasingly difficult.
Low power design is a collection of techniques and methodologies aimed at reducing the overall dynamic and static power consumption of an integrated circuit IC. Looking at the individual components of power as illustrated by the equation in Figure 1 , the goal of low power design is to reduce the individual components of power as much as possible, thereby reducing the overall power consumption. The power equation contains components for dynamic and static power. Dynamic power is comprised of switching and short-circuit power; whereas static power is comprised of leakage, or current that flows through the transistor when there is no activity. The value of each power component is related to any of the following factors:. For example, the higher the voltage, the higher the power consumed by each component, resulting in higher overall power.
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DIGITAL SYSTEM CLOCKING. High-Performance and Low-Power Aspects
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